# crossbar array Projects at AI Tinkerers

> Canonical HTML: https://aitinkerers.org/technologies/crossbar-array
> Markdown URL: https://aitinkerers.org/technologies/crossbar-array.md
> Technology record last updated: 2026-03-10T10:15:45Z
> Generated: 2026-09-21T04:43:01Z

A high-density, two-terminal grid architecture: it integrates memory and processing at each cross-point, directly accelerating vector-matrix multiplication (VMM) for AI and neuromorphic computing.

The crossbar array is a foundational architecture for in-memory computing (IMC), directly addressing the von Neumann bottleneck. It uses a dense grid of perpendicular nanowires: a non-volatile memory element (like a memristor or RRAM cell) sits at each intersection, storing data as resistance. This allows for parallel, analog computation, executing the critical vector-matrix multiplication (VMM) operation by leveraging Ohm’s and Kirchhoff’s laws. To ensure reliable operation and prevent 'sneak-path' current, advanced configurations like the 1T1M (1-transistor-1-memristor) or 1S1R (1-selector-1-resistor) schemes are often employed. We're seeing real-world density: researchers have demonstrated arrays with a $4.5$ terabits per square inch packing density, proving its potential for next-generation, ultra-efficient hardware.

- Official technology site: https://crossbar-inc.com/
- Public AI Tinkerers demos and talks: 1
- Result page: 1 of 1

## Recent Public Talks and Demos

### [From Bits to Volts: Achieving Faster and Greener AI Inference with Plug-in Analog Neural Hardware](https://nyc.aitinkerers.org/talks/rsvp_BfRCkMX1Vbw)

The AI infrastructure of tomorrow demands breakthroughs beyond power-hungry GPUs. This talk unveils a revolutionary plug-in hardware module that performs neural network inference using analog computation, slashing power consumption by 100–1000× and latency by up to 100,000× compared to digital accelerators. By encoding weights and biases as voltages and currents, our device computes at the speed of physics, enabling near-instantaneous inference with minimal energy. We’ll showcase SPICE-model validation proving digital equivalence, a roadmap from PCB prototype to ASIC implementation, and real-world use cases like edge AI, drones, and data-center acceleration. Discover how analog neural hardware redefines efficiency, making low-latency, low-power AI deployable anywhere, from IoT to defense. Join us to see the future of inference infrastructure.

- Event context: The Future of AI Infrastructure (Ft. Oracle & NVIDIA) — 2025-12-09 — New York City
- Public talk page: https://nyc.aitinkerers.org/talks/rsvp_BfRCkMX1Vbw

## Related Technologies

- [ASIC](https://aitinkerers.org/technologies/asic) ([Markdown](https://aitinkerers.org/technologies/asic.md)) — 1 public demo
- [memristor](https://aitinkerers.org/technologies/memristor) ([Markdown](https://aitinkerers.org/technologies/memristor.md)) — 1 public demo
- [op-amp](https://aitinkerers.org/technologies/op-amp) ([Markdown](https://aitinkerers.org/technologies/op-amp.md)) — 1 public demo
- [SPICE](https://aitinkerers.org/technologies/spice) ([Markdown](https://aitinkerers.org/technologies/spice.md)) — 1 public demo