# memristor Projects at AI Tinkerers

> Canonical HTML: https://aitinkerers.org/technologies/memristor
> Markdown URL: https://aitinkerers.org/technologies/memristor.md
> Technology record last updated: 2026-03-10T10:15:45Z
> Generated: 2026-09-22T12:38:20Z

A non-volatile, two-terminal passive component: its resistance (memristance) is not fixed, but dynamically 'remembers' the history of charge that has flowed through it.

The memristor is the fourth fundamental passive circuit element, theoretically predicted by electrical engineer Leon Chua in 1971. It functions as a 'memory resistor,' maintaining its resistance state (a binary 0 or 1) even after power is removed (non-volatile memory). HP Labs, led by R. Stanley Williams, physically demonstrated the first stable prototype in 2008 using a thin film of titanium dioxide ($\text{TiO}_2$). This technology is now critical for next-generation computing: it enables high-density, low-power resistive random-access memory (RRAM) and is a core component for advanced neuromorphic (brain-like) computing architectures.

- Official technology site: https://en.wikipedia.org/wiki/Memristor
- Public AI Tinkerers demos and talks: 1
- Result page: 1 of 1

## Recent Public Talks and Demos

### [From Bits to Volts: Achieving Faster and Greener AI Inference with Plug-in Analog Neural Hardware](https://nyc.aitinkerers.org/talks/rsvp_BfRCkMX1Vbw)

The AI infrastructure of tomorrow demands breakthroughs beyond power-hungry GPUs. This talk unveils a revolutionary plug-in hardware module that performs neural network inference using analog computation, slashing power consumption by 100–1000× and latency by up to 100,000× compared to digital accelerators. By encoding weights and biases as voltages and currents, our device computes at the speed of physics, enabling near-instantaneous inference with minimal energy. We’ll showcase SPICE-model validation proving digital equivalence, a roadmap from PCB prototype to ASIC implementation, and real-world use cases like edge AI, drones, and data-center acceleration. Discover how analog neural hardware redefines efficiency, making low-latency, low-power AI deployable anywhere, from IoT to defense. Join us to see the future of inference infrastructure.

- Event context: The Future of AI Infrastructure (Ft. Oracle & NVIDIA) — 2025-12-09 — New York City
- Public talk page: https://nyc.aitinkerers.org/talks/rsvp_BfRCkMX1Vbw

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